Semiconductor devices may be fabricated on the surface of a semiconductor wafer in layers and later singulated after wafer probe into individual chips. The individual chips thus fabricated are subjected to a series of tests to determine if the chips function properly both before (at wafer probe) and after being singulated (e.g., package test). These tests are sometimes repeated at several points in the manufacturing process, since the steps involved in singulating and packaging the chips can result in thermal and mechanical stresses which can induce failures of individual chips. The tests are designed to identify parts that are actually failing when tested, a failure sometimes referred to as a “time-zero” failure.
But many failures that occur in semiconductor chips are not “time-zero” failures, but instead failures that occur later after the chips have been in operation for a short time. These failures, sometimes referred to as “infant-mortality” or “early” failures, are sometimes identified through the use of a “burn-in” process, in which the chips are operated for an extended period (compared to the duration of normal production testing) beyond the electrical and environmental ranges defined by the design engineers for normal operation. This operational test period may identify a significant number of failures, but this is accomplished at the expense of the additional cost of testing, as well as a slightly reduced intrinsic life expectancy of the chips tested that go on to use in the field.
Some manufacturers have used a “no burn-in” approach, using time-zero failures to predict early failures without a production burn-in. Using time-zero failures to predict marginal chips, however, does not always predict failures of chips that are defective. These unpredicted “statistical outliers” tend to increase in number as the dimensions of the semiconductor structures within the chips decrease driving increased variance, and are thus not reliably predicted by time-zero-based non burn-in techniques when applied to many of today's sub-micron semiconductor devices.
Analysis of devices that have actually failed can provide an improved statistical basis for identifying statistical outliers. However, known outlier screening techniques are either not sufficient or not applicable to the given domain to attain some required product quality levels. Improved outlier identification algorithms are needed to minimize scrap or downgrade material, and monitor disposition in operations such as wafer probe and package test. As process variance continues to increase at every new technology node, new outlier screening techniques that more highly correlate outlier material to defective material are needed for burn-in reduction or elimination and to improve quality by scrapping outlier devices which can reduce the test cost and provide lower defect rates (e.g., defective parts per million (DPPM)).